Every electrical value is lifted from the PDF and pinned to the page it came from, then checked by the applicable subset of its current registry of implemented xERC rule IDs. Missing evidence stays visible — it never becomes a silent pass.
Pick one path. The workspace makes the next evidence and review step explicit before it generates anything.
Tell us the job, power source, and key features. We open a fresh project, find candidate parts, then keep source evidence and your review in the loop.
What happens next: candidate parts are suggestions, not design approval. You inspect the cited data and sign off before moving forward.
Start with the exact parts you already know. Add their datasheet PDFs in a project so electrical limits, pinouts, and application circuits can be checked against their source pages.
Open component workspaceCurrent scope: PDF extraction is supported. A BOM is useful for selecting exact parts, but BOM/CSV upload is not yet a one-click project import.
Open a project, then use the engineering workspace to inspect a KiCad board file alongside evidence and named-connectivity checks.
Open workspace to inspect itCurrent scope: this landing path inspects .kicad_pcb files read-only. In the workspace, a project-bound, source/parity-checked pre-routing footprint-placement draft is available; full KiCad-project import, routing, and interactive board editing are not.
xERC has a current registry of implemented rule IDs and evaluates the applicable subset when the design carries the required evidence. Findings and checks that could not be evaluated remain numbered, sourced, and visible for closure.
Datasheet-to-schematic, electrical-rules checking, and exports — answered.
Yes. It extracts a chip's datasheet PDF into a verified, machine-readable electrical model, then generates a support-circuit schematic from that model — exportable to KiCad, Zener, and firmware scaffolds.
It runs in your browser with no install. Customer-project and paid processing endpoints may require an API key on a hosted deployment.
We measure ~0.92 extraction accuracy on graded parts (n=9), and we show our work: every extracted value is cited to its source page and bounding box, so you can verify it yourself. Nothing is marked gold until an engineer signs off. We don't claim 100%.
xERC is a cross-design electrical-rules check covering abs-max envelopes, decoupling, I²C pull-ups, floating pins, component derating, exposed-pad connectivity, and package/pinout consistency. Each finding carries its source or engineering basis; physical PCB checks remain external.
Yes. KiCad and Altium netlists import; KiCad (.kicad_sch), Zener (.zen), firmware scaffolds, and the raw Design JSON export.
Yes. Alternates are scored on footprint, interfaces, supply range, and abs-max, then classified drop-in, review-needed, or blocked — with optional live stock, price, and lifecycle from distributor APIs.
Flux.ai and Circuit Mind generate circuits from a prompt or a requirements list — you have to trust the output. RapidCircuitry grounds everything in the actual datasheet: page-cited, verifiable, with a live xERC safety net and a human sign-off gate instead of a black-box answer.
It checks available MLCC DC-bias, voltage/power derating, exposed-pad connectivity, and package/pinout evidence. Physical land-pattern geometry, placement, routing, creepage, and manufacturability still require PCB-layout DRC/DFM and review.
Yes — a Zephyr devicetree overlay and a C pin/address header generated from the verified pinout, matching the schematic by construction.
No. Open the workspace, bring a datasheet PDF, and run the full extract, verify, and xERC pipeline in the browser.
No install, no signup to look. Watch the whole safety net work on your own part.